Simple DAB transmitter

 

Introduciton

This page describes hardware for digital USB DAB transmitter. If u are looking for modulator which utilizes less CPU cycles, take a look at EasyDABv1-USB and EasyDABv2-Ethernet modulators, which is using FPGA for signal processing.

  • Nominal Transmit Frequency: 3 ... 206 Mhz (with current PLL loop filter).
  • Maximal Tramsmit Frequency: 400 MHz (with 1Ghz reference clock).
  • Transmit Power:                 -60 ... 5 dBm.
  • Drivers Installation Needed:     Yes
  • Software Needed:                 CRC-mmbtools (multiplexer + modulator)
  • LEDs That shows state: Yes (underflow, PLL-lock)
  • I/Q samples width: 16 bit
  • Complex sample rate: 2048 kS/s.
  • External power needed: No

 

Hardware Description

dab-tx block diagram

This is the block diagram, that illustrates transmitter design. The AD9957 chip contains 1GSPS DAC this allows to produce signal up to 400 MHz. In current configuration the maximum transmission frequency - is 206 MHz. The FX2 hardware getting 16bit I/Q samples from USB BULK transfers and sending them to AD9957 chip, where it digitally upconverted to specified frequency. The maximal bandwidth of baseband signal for current registers configuration - is 2,048Mhz. Device can be used not only for DAB-transmission, but for DRM+/FM/DVB or other modulation too.

The AD9957 in quadrature upconverter mode:

AD9957 QDUC MODE

ad9957 qduc 

The half-band filters (4x) and interpolators (63x) are enabled, this allows to configure PDCLK clock rate to 516096/(2x63) = 4096 KHz (it's for I/Q samples).

The Quartz crystal used in AD9957 schematic - is 24,576 MHz. This quartz is choosed to lock internal PLL for system clock rate to: 24576 * 21 = 516096 KHz.

 

Schematic and PCB 

Here is sample of FX2 board: http://oscar.dcarr.org/ssrp/hardware/usb/usb.php

This board is configured to use single endpoint (EP2) in 1024 Bytes mode with 4x buffering (NOTE: sometimes it's not enough for HI-Speed USB transferring). So you must monitor level in TxENABLE pin (it must be always low in normal transfer mode), if it have "1" sometimes - then try to change PC (with better performance), or remove other USB-devices, or in worst case - you need to add fifo buffer between boards (see TODO).

My FX2 board looks like this:

fx2 board

2). The AD9957 prototype board looks like this:

ad9957 top  ad9957 bot

 

Connected boards:

 

AD9957 Board's schematic (corrected):

schematic

schematic

Interconnection between FX2 and AD9957 boards:

AD9957 Pin Name

Cypress FX2 Pin Name

Type

Description

GND

GND

Ground

 

-

Vcc

Power

3.3V max 0.3A

-

SDA

Open Drain

Data for I2C compatible interface ,2.2k pull-up resistor is connected to Vcc

-

SCL

Open Drain

Clock for I2C compatible interface ,2.2k pull-up resistor is connected to Vcc

-

IFCLK

I/O/Z

Interface Clock. use for synchronously clocking data into or out of the slave FIFOs

-

CTL0/FLAGA

Output

GPIF control Output; Programmable slave-FIFO output status flag signal

-

CTL1/FLAGB

Output

GPIF control Output; Programmable slave-FIFO output status flag signal

TxENABLE

CTL2/FLAGC

Output

GPIF control Output; Programmable slave-FIFO output status flag signal

SDIO

PA0/INT0

I/O/Z

Bidirectional I/O port A pin; Active-low 8051 interrupt input signal

I/O_UPDATE

PA1/INT1

I/O/Z

Bidirectional I/O port A pin; Active-low 8051 interrupt input signal

-

PA2/SLOE (connected to 3.3V)

I/O/Z

Bidirectional I/O port A pin; Output enable for the slave FIFO connected to FD[0-15]

SCLK

PA3/WU2

I/O/Z

Bidirectional I/O port A pin; USB wake up

-

PA4/FIFOADR0 (connected to GND)

I/O/Z

Bidirectional I/O port A pin; Address select for the slave FIFO connected to FD[0-15]

-

PA5/FIFOADR1 (connected to GND)

I/O/Z

Bidirectional I/O port A pin; Address select for the slave FIFO connected to FD[0-15]

-

PA6/PKTEND (connected to GND)

I/O/Z

Bidirectional I/O port A pin; Packet end for the slave FIFO connected to FD[0-7/15]

*CS + I/O_RESET

PA7/FLAGD/SLCS

I/O/Z

Bidirectional I/O port A pin; Slave FIFO enable or output status flag signal

-

RESET

Input

Active low reset. Resets entire chip

-

WAKEUP

Input

USB wake up, starts oscillator, interrupts and exits the suspend mode

D0 + D1 + D2

PB0/FD0

I/O/Z

Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus

D3

PB1/FD1

I/O/Z

Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus

D4

PB2/FD2

I/O/Z

Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus

D5

PB3/FD3

I/O/Z

Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus

D6

PB4/FD4

I/O/Z

Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus

D7

PB5/FD5

I/O/Z

Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus

D8

PB6/FD6

I/O/Z

Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus

D9

PB7/FD7

I/O/Z

Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus

D10

PD0/FD8

I/O/Z

Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus

D11

PD1/FD9

I/O/Z

Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus

D12

PD2/FD10

I/O/Z

Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus

D13

PD3/FD11

I/O/Z

Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus

D14

PD4/FD12

I/O/Z

Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus

D15

PD5/FD13

I/O/Z

Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus

D16

PD6/FD14

I/O/Z

Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus

D17

PD7/FD15

I/O/Z

Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus

-

CLKOUT

O/Z

12-24-48 MHz clock, phase locked to the 24MHz  input clock

PDCLK

RDY0/SLRD

Input

GPIF input signal; Read strobe for the slave FIFOs connected to FD[0-7/15]

-

RDY1/SLWR

Input

GPIF input signal; Write strobe for the slave FIFOs connected to FD[0-7/15]

JP2 +5V

USB 5V

Power

5V max 0.5A

 

SOFTWARE AND OTHER FILES:

Eagle project for AD9957 test board only: ad9957board.zip (schematic - is ok, but on pcb - there is few conductor are not routed).

Firmware and stand-alone sampling-player software: sdr-dac3.tar.gz (this firmware based on SSRP project).

ChangeLog:

  • Control and Data interfaces are splitted in firmware now (this needs for gnuradio).

GNURadio modulegr-ssrptx.tar.gz (github repo: gr-ssrptx). This block is tested and works fine with multiple-stations FM-transmission simulation, dscribed at opendigitalradio page. As additional parameters to GNURadio block you can set:

  • Output frequency in hertz.
  • Amplitude scale factor [0.0 ... 2.0]

The input format of samples is "sc16" - short complex 16, with fixed samplerate of 2048 kS/s.

 

 

 Video demonstration:

 

TODO:

  1. Enable PDCLK only if we have properly aligned buffer.
  2. Add FIFO between boards. Due sometimes internal 4Kb buffer is not enough, especially on laptops.
  3. Add GNURadio sink module. (done)
  4. Replace FX2 board by ATSAM3U or LPC1800 ´╗┐AVnet's Xilinx Spartan-6 FPGA LX9 MicroBoard (89$)
  5. Move crc-dabmod modulation algo into FPGA using simulink/system generator.
  6. Use Microboard's ethernet interface as ETI-receiver and web-interface for DAB transmitter configuration.
  7. Try to implement DVB-T/T2 transmission.

Board with both chips:

      

Eagle project ad9957board.tar.gz (NOTE: this pcb is not tested in real-world).´╗┐

KNOWN PROBLEMS:

  • 4096 bytes fifo may be not enough for 2048 kS/s in 16bit mode on slow PC's.
  • Sometimes (once from 20 tries) I/Q samples may be swapped due PDCLK may strobes when fc2 mcu not yet set data pins. This is cost of design simplification. The result that you'll have - is inversed spectrum.