Index of /downloads/hardware/DAB-TX/Spartan6-FPGA/hls

[ICO]NameLast modifiedSizeDescription

[PARENTDIR]Parent Directory  -  
[   ]qpsk_mapper_freq_interleaver_s6.zip2015-05-04 11:47 523K 
[   ]pre_fft_preorder_converter1536_2048_s6.zip2015-05-04 11:47 896K 
[   ]input_interface_s6.zip2015-05-04 11:46 119K 
[   ]gain_control_s6.zip2015-05-04 11:46 2.9M 
[   ]dqpsk_prbs_null2_s6.zip2015-05-04 11:47 911K 
[TXT]README.txt2015-05-04 11:57 236  
[TXT]LICENSE.txt2015-05-04 11:09 954  
[   ]HLS_sources-05.01.2017.tar.gz2017-02-03 23:48 1.7M 

Please take a note, that testing applications are not producing proper results,
since actual logic source code has been changed multiple times.
So running C simulation may fail. But running C Synthesis and exporting RTL are
works fine.