easydabv2_8192 Project Status (02/05/2016 - 13:00:03)
Project File: easydabv2.8192.xise Parser Errors: No Errors
Module Name: easydabv2_8192 Implementation State: Programming File Generated
Target Device: xc6slx9-2tqg144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
72 Warnings (4 new)
Design Goal: Area Reduction
  • Routing Results:
All Signals Completely Routed
Design Strategy: strategy2
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 4,724 11,440 41%  
    Number used as Flip Flops 4,720      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 4      
Number of Slice LUTs 4,711 5,720 82%  
    Number used as logic 3,938 5,720 68%  
        Number using O6 output only 2,641      
        Number using O5 output only 152      
        Number using O5 and O6 1,145      
        Number used as ROM 0      
    Number used as Memory 464 1,440 32%  
        Number used as Dual Port RAM 28      
            Number using O6 output only 0      
            Number using O5 output only 0      
            Number using O5 and O6 28      
        Number used as Single Port RAM 40      
            Number using O6 output only 32      
            Number using O5 output only 0      
            Number using O5 and O6 8      
        Number used as Shift Register 396      
            Number using O6 output only 83      
            Number using O5 output only 0      
            Number using O5 and O6 313      
    Number used exclusively as route-thrus 309      
        Number with same-slice register load 254      
        Number with same-slice carry load 55      
        Number with other load 0      
Number of occupied Slices 1,414 1,430 98%  
Number of MUXCYs used 732 2,860 25%  
Number of LUT Flip Flop pairs used 5,066      
    Number with an unused Flip Flop 1,290 5,066 25%  
    Number with an unused LUT 355 5,066 7%  
    Number of fully used LUT-FF pairs 3,421 5,066 67%  
    Number of unique control sets 384      
    Number of slice register sites lost
        to control set restrictions
1,451 11,440 12%  
Number of bonded IOBs 64 102 62%  
    Number of LOCed IOBs 64 64 100%  
    IOB Flip Flops 10      
Number of RAMB16BWERs 29 32 90%  
Number of RAMB8BWERs 6 64 9%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 3 16 18%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 1 4 25%  
    Number used as DCMs 1      
    Number used as DCM_CLKGENs 0      
Number of ILOGIC2/ISERDES2s 1 200 1%  
    Number used as ILOGIC2s 1      
    Number used as ISERDES2s 0      
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 9 200 4%  
    Number used as OLOGIC2s 9      
    Number used as OSERDES2s 0      
Number of BSCANs 1 4 25%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 7 16 43%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.68      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Feb 5 17:19:27 2016014 Warnings (0 new)51 Infos (0 new)
Translation ReportCurrentFri Feb 5 17:19:36 2016053 Warnings (4 new)1 Info (0 new)
Map ReportCurrentFri Feb 5 17:21:42 201602 Warnings (0 new)8 Infos (0 new)
Place and Route ReportCurrentFri Feb 5 17:22:53 201601 Warning (0 new)0
Power Report     
Post-PAR Static Timing ReportCurrentFri Feb 5 17:23:06 201601 Warning (0 new)3 Infos (0 new)
Bitgen ReportCurrentFri Feb 5 17:23:27 201601 Warning (0 new)2 Infos (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentFri Feb 5 17:23:28 2016
WebTalk Log FileCurrentFri Feb 5 17:23:29 2016

Date Generated: 02/15/2016 - 10:48:10